1. Field of the Invention
The present invention generally relates to an asynchronous transfer mode (ATM) apparatus which multiplexes and demultiplexes ATM cells, and more particularly to an ATM apparatus configured so that a plurality of ATM apparatuses which send and receive ATM cells through a Level 2 UTOPIA interface are connected in a hierarchical formation.
The ATM Forum Technical Committee proposes the Level 2 UTOPIA interface (UTOPIA)is an abbreviation of the Universal Test and Operations PHY Interface for ATM. The Level 2 UTOPIA interface prescribes an interface between an ATM layer device and a PHY (physical) layer device. More particularly, the Level 2 UTOPIA interface defines a single-stage structure in which a plurality of PHY layer devices are connected to a single ATM layer device. The maximum number of PHY layer devices connectable to the ATM layer device is equal to eight for 155 Mbps, and four for 622 Mbps. Hence, only a limited number of subscribers connected to the PHY layer devices can be accommodated in the single-stage structure.
2. Description of the Related Art
FIGS. 1 and 2 show a network system equipped with an ATM apparatus which performs multiplexing and demultiplexing of ATM cells. Referring to FIG. 1, the system includes in-house devices 13-1 of subscribers #1-#N, terminal devices 13-11, network terminals 13-12, and an office station 13-2. The office station 13-2 includes an ATM switch 13-21, an access network device 13-22, and an operation system part (OPS) 13-2. Referring to FIG. 2, a cabinet 14-1 is connected to the office station 13-2, which includes the ATM switch 13-21. The cabinet 14-1 includes an access network device 14-11 and an operating system part 14-12.
The network system shown in FIGS. 1 and 2 is a network system which employs an asymmetrical digital subscriber line (abbreviated as ADSL) transmission system. The ADSL transmission system is promising as a transmission system capable of sending data to the subscribers at high speed, such as digital communications through the Internet.
The access network devices 13-22 and 14-11 receive data received via the asymmetrical digital subscriber lines from the terminal devices 13-11 in the subscriber houses, and multiplex the received data in a cell multiplexing fashion. Then, the access network devices 13-22 and 14-11 send the cell-multiplexed data to the ATM switch 13-21 via an optical fiber. Further, the access network devices 13-22 and 14-11 demultiplex cell-multiplexed data transmitted from the ATM switch 13-21 via the optical fiber, and distribute demultiplexed data to the subscriber terminals 13-1 via the asymmetrical digital subscriber lines. Hence, the access network devices 13-22 and 14-11 are ATM apparatuses that perform ATM cell processes such as multiplexing and demultiplexing of a large number of ATM cells.
FIG. 3 illustrates a structure of the access network device 13-22 or 14-11. The access network device includes asymmetrical digital subscriber line (ADSL) packages (cards) 15-1, a control package 15-2 and a 155 Mbps interface package 15-3. Each of the ADSL packages 15-1 is made up of asymmetrical digital subscriber line terminating devices (ATU-C) 15-11, and a cell multiplexing/demultiplexing device 15-12. The control package 15-2 includes a cell multiplexing/demultiplexing device 15-21, an ATM switch chip 15-22, a central processing unit (CPU) 15-23, an Ethernet interface part 15-24, and a cell multiplexing/demultiplexing device 15-25. The ATM switch chip 15-22 includes a routing table 15-221. The 155 Mbps interface package 15-3 includes an SDH terminating part (STM-1) 15-31 and an optical module 15-32.
In each of the ADSL packages 15-1, the cell multiplexing/demultiplexing device 15-12 respectively send data received from the asymmetrical digital subscriber lines to the cell multiplexing/demultiplexing device 15-12, which multiplexes the received data in the cell multiplexing formation. Then, the cell-multiplexed data is output to the control package 15-2. Cell-multiplexed data output from the control package 15-2 is demultiplexed by the cell multiplexing/demultiplexing device 15-12 in each of the ADSL packages 15-1. The multiplexed data are then sent to the asymmetrical digital subscriber lines.
In the control package 15-2, the cell multiplexing/demultiplexing device 15-21 further multiplexes the cell-multiplexed data output from the ADSL packages 15-1, and send the resultant cell-multiplexed data to the ATM switch chip 15-22. Further, the cell multiplexing/demultiplexing device 15-21 demultiplexes cell-multiplexed data output from the ATM switch chip 15-22, and send demultiplexed cell data to the ADSL packages 15-1.
Further, the cell multiplexing/demultiplexing device 15-25 multiplexes cell-multiplexed data output from the 155 Mbps interface package 15-3, and send the resultant cell-multiplexed data to the ATM switch chip 15-22. Further, the cell multiplexing/demultiplexing device 15-25 demultiplexes cell-multiplexed data output from the ATM switch chip 15-22, and send demultiplexed cell data to the 155 Mbps interface package 15-3.
The ATM Forum proposes an interface between the ATM layer device and the PHY layer device as a standardized interface in the ATM apparatuses that perform cell multiplexing and demultiplexing. Such a standardized interface is called UTOPIA.
The ATM Forum proposes some levels of UTOPIA. The Level 2 UTOPIA interface defines the interface of the single-stage structure in which a plurality of PHY layer devices are connected to a single ATM layer device (The ATM Forum Technical Committee xe2x80x9cUtopia Level 2, v1.0xe2x80x9d, af-phy-0039.000, June 1995, the disclosure of which is hereby incorporated by reference).
The Level 2 UTOPIA interface describes the following three definitions regarding the number of PHY layer devices, the cell format and the signal transmit and receive operation.
According to the first definition, the number of PHY layer devices that is allowed to be connected to one ATM layer device is limited up to eight when the transmission rate of the ATM layer is equal to 155 Mbps, and is limited up to four for 622 Mbps. 16 address spaces are allowed, and the upper limit on the number of address spaces is equal to 16 in practice.
The second definition prescribes two types of cell formats, one of which is a cell format in 8-bit mode and the other is a cell format in 16-bit mode. A user defined field (UDF) in the cell formats can be open to the user.
FIGS. 4A and 4B respectively 8-bit mode and 16-bit mode cell formats in the Level 2 UTOPIA interface. As shown in FIG. 4A, the 8-bit mode cell format is made up of four headers #1-#4, the user defined area UDF and 48 payload fields #1-#48. As shown in FIG. 4B, the 16-bit mode cell format is made up of four headers #1-#4, two user defined fields #1 and #2, and 48 payload fields #1-#48. As described above, the user is free to define the user defined field UDF of the 8-bit and the user defined fields UDF#1 and UDF#2 of the 16-bit mode.
The third definition prescribes the signal transmit and receive operation between one ATM layer device and a plurality of PHY layer devices (Multi-PHY). The signal transmit and receive operation uses one transmit-cell available signal 1TxClav and one receive-cell available signal 1RxClav. The third definition allows a direct status indication and a multiplexed status polling to be arbitrarily chosen.
A description will now be given, with reference to FIGS. 5 through 8, of the transmit and receive operation with the signals 1TxClav and 1RxClav.
FIG. 5 shows connections of signal lines between one ATM layer device 17-2 and a plurality of PHY layer devices 17-1 (#1-#N). FIG. 5 illustrates an arrangement in the 8-bit mode. The signal lines between the ATM layer device 17-2 and the PHY layer devices 17-1 has a bus connection format. Signals between the ATM layer devices and the PHY layer devices are as shown in FIGS. 6A and 6B.
FIGS. 6A and 6B show signal lines of the Level 2 UTOPIA interface. More particularly, FIG. 6A shows signals used when the ATM layer device 17-2 sends cell data to the PHY layer devices 17-1. FIG. 6B shows signals used when the ATM layer device receives cell data from the PHY layer devices 17-1.
TxAddr is a five-bit address signal for selecting the PHY layer device 17-1 to which cell data is to be transferred, and is sent to the PHY layer devices 17-1 from the ATM layer device 17-2.
TxData is a transmit data signal sent to the PHY layer devices 17-1 from the ATM layer device 17-2. The TxData uses eight transmit data bus lines TxData [7:0] in the 8 bit mode, and further uses extended bus lines TxData [15:8] in the 16-bit mode.
TxSOC is a start-of-transmit-cell signal, and is sent to the PHY layer devices 17-1 from the ATM layer device 17-2. TxEnb* is a transfer enable signal for a transmit cell, and is sent to the PHY layer devices 17-1 from the ATM layer device 17-2 during a transmit cell transfer period. The symbol xe2x80x9c*xe2x80x9d denotes the negative logic, which holds true for signals described below.
TxFull*/TxClav is a signal indicating the state of a cell storage buffer in the PHY layer device 17-1, and is sent to the ATM layer device 17-2 from the PHY layer device 17-1.
TxFull* is a signal used when cells are sent on the octet basis, and is sent when an FIFO buffer on the octet basis is full of cells and has no available area. TxClav is a signal used when cells are sent on the cell basis, and is sent when the cell buffer has an idle area for storing a cell.
TxClk is a transmit clock signal sent from the ATM layer device 17-2 to the PHY layer devices 17-1, which perform the transmit and receive operation in synchronism with the transmit clock signal.
TxPrty is an odd parity signal for the transmit data signal TxData, and is sent to the PHY layer devices 17-1 from the ATM layer device 17-2. TxRef is a reference signal, which is sent to the PHY layer devices 17-1 from the ATM layer device 17-2.
RxAddr is a five-bit receive address signal for selecting the PHY layer device 17-1 from which cells are sent to the ATM layer device 17-2, and is sent to the ATM layer device 17-2 from the PHY layer device 17-1.
RxData is a receive data signal which the ATM layer device 17-1 receives from the PHY layer devices 17-1. The signal RxData occupies eight receive data bus lines [7:0] in the 8-bit mode, and further uses extended data bus lines RxData [15:81] in the 16-bit mode.
RxSOC is a start-of-receive-cell signal, which is sent to the ATM layer device 17-2 from the PHY layer devices 17-1. RxEnb* is a transfer enable signal for a receive cell, and is sent from the ATM layer device 17-2 to the PHY layer devices 17-1 during a cell receive period.
RxEmpty*/RxClav is a signal indicating the state of a cell send buffer in the PHY layer device 17-1, and is sent to the ATM layer device 17-2 from the PHY layer devices 17-1.
RxEmpty* is a signal used when cells are received on the octet basis, and is sent when the FIFO buffer on the octet basis is idle and there is no cell sent by the PHY layer device 17-1. RxClav is a signal used when cells are received on the cell basis, and is sent when there is a cell queued in the cell buffer.
RxClk is a receive clock signal sent to the PHY layer devices from the ATM layer device 17-2. The PHY layer devices perform the signal receive and transmit operation in synchronism with the clock signal RxClk.
RxPrty is an odd parity signal for the receive data signal RxData, and is sent to the ATM layer device 17-2 from the PHY layer devices 17-1. RxRef is a reference signal, which is sent to the ATM layer device 17-2 from the PHY layer devices 17-1.
FIG. 7 is a timing chart of the transmit operation in the Level 2 UTOPIA interface. In the transmit operation shown in FIG. 7, cell data is transferred from the ATM layer device to the PHY layer device.
Referring to FIG. 7, cells are transmitted to the Nth PHY layer device #N until the eighth rising edge of the transmit clock signal TxClk, as shown in part (h) of FIG. 7. As shown in part (f) of FIG. 7, the 42th payload P42 to the 48th payload P48 of the data signal of the cell being transmitted are sent in synchronism with the rising edges of the transmit clock signal TxClk. The Nth PHY layer device #N latches the data signal of the cell in synchronism with the rising edges of the transmit clock signal TxClk. While the data signal of the cell is being transferred, as shown in part (a) of FIG. 7, a polling operation for selecting the PHY layer device which transmits the next cell is performed.
As shown in part (c) of FIG. 7, the polling operation commences sending, as the transmit address signal TxAddr, the address of the PHY layer device which is a candidate for the next transmit destination. As shown in part (d) of FIG. 7, the PHY layer device specified by the above address signal informs, in the next clock cycle, the ATM layer device of the state of its own cell storage buffer by the signal TxClav.
Referring to parts (c) and (d) of FIG. 7, the (Nxe2x88x921)th PHY layer device sends out a signal indicating that the cell storage buffer is not available (this signal is set to the low level) in response to the first rising edge of the transmit clock signal TxClk (hereinafter, the first rising edge is denoted as TxClk1). The ATM layer device recognizes that the cell storage buffer of the (Nxe2x88x921)th PHY layer device cannot be used.
In response to TxClk2, the ATM layer device selects the address of the (N+3)th PHY layer device, which sends out, in the next clock cycle, that is, in response to TxClk3, a signal indicating that the cell storage buffer is available (the signal is switched to the high level). The ATM layer device recognizes that the cell storage buffer of the (N+3)th PHY layer device is available.
Similarly, in response to TxClk4, the ATM layer device selects the address of the (N+1)th PHY layer device, which sends out the signal that the cell storage buffer is not available in response to TxClk5. In response to TxClk6, the ATM layer device selects the address of the Nth PHY layer device, which sends out that the cell storage buffer is available in response to TxClk7.
Hence, during the period of polling, the ATM layer device recognizes that the (N+3)th and Nth PHY layer devices can queue the next cell. In part (c) of FIG. 7, 1F denotes a null address, and none of the PHY layer devices respond to the null address 1F.
When the 48th payload P48 is completely transmitted, as shown in part (e) of FIG. 7, the ATM layer device stops sending the transfer enable signal TxEnb* in response to TxClk8 (the signal TxEnb* is switched to the high level), and thus causes the PHY layer device to stop queuing the cell data. At that time, that is, in response to TxClk8, as shown in part (c) of FIG. 7, the ATM layer device sends out the address N+3 of the next destination PHY layer device.
The (N+3)th PHY layer device detects that the transfer enable signal TxEnb* is stopped in response to TxClk9 (switches to the high level) and the address signal of the (N+3)th PHY layer device is sent out as the address signal, and recognizes that cell data addressed to itself (N+3)th PHY layer device will be transmitted for the next time. Then, the (N+3)th PHY layer device latches cell data from the transmit data signal line TxData.
The PHY layer devices having the addresses other than the address sent out in response to TxClk9 do not latch the cell data from the transmit data signal line TxData. In the above-mentioned manner, the transmit destination PHY layer device is selected in response to TxClk9.
In response to TxClk9, as shown in part (e) of FIG. 7, the ATM layer device sends out the transfer enable signal TxEnb* (switches to the low level). Then, as shown in part (f) of FIG. 7, the next cell is sent out in the order of headers H1, H2, H3 and H4. Also, the signal TxSOC indicative of start of cell is sent out as shown in part (g) of FIG. 7.
The PHY layer device #N+3 thus selected queues, as cell data, the signal from the transmit data signal line TxData during the time when the transfer enable signal TxEnB* is being sent out (as long as it is at the low level). Further, during the above period, the polling is started again in synchronism with TxClk10 (which denotes the tenth rising edge of the transmit clock signal TxClk).
FIG. 8 is a time chart of the receive operation in the Level 2 UTOPIA interface. In the receive operation shown in FIG. 8, cell data is transferred to the PHY layer devices to the ATM layer device.
As shown in part (h) of FIG. 8, cell data is received from the Nth PHY layer device #N until the ninth rising edge of the receive clock signal RxClk (expressed as RxClk9). As shown in part (f) of FIG. 8, the data being received is the 41th payload P42 to the 48th payload P48 sent in synchronism with the rising edges of the receive clock signal RxClk. While the above cell data is being received, as shown in part (a) of FIG. 8, a polling operation for selecting the transmission source PHY layer device from which cell data will be received for the next time.
As shown in part (c) of FIG. 8, the polling operation commences sending, as the receive address signal RxAddr, the address of the PHY layer device which is a candidate for the next receive source from which cell will be received. As shown in part (d) of FIG. 8, the PHY layer device specified by the above address signal sends out the signal RxClav during the next clock cycle, and thus informs the ATM layer device of the state of a cell send-out buffer of the above PHY layer device.
Referring to parts (c) and (d) of FIG. 8, the (N=1)th PHY layer device sends out a signal indicating that the cell send-out buffer is not available (this signal is set to the low level) in response to the first rising edge of the receive clock signal (RxClk1). The ATM layer device recognizes that the cell send-out buffer of the (Nxe2x88x921)th PHY layer device cannot be used.
In response to RxClk2, the ATM layer device selects the address of the (N+3)th PHY layer device, which sends out, in the next clock cycle, that is, in response to RxClk3, a signal indicating that the cell send-out buffer is available (the signal is switched to the high level). The ATM layer device recognizes that the cell send-out buffer of the (N+3)th PHY layer device is available.
Similarly, in response to RxClk4, the ATM layer device selects the address of the (N+1)th PHY layer device, which sends out the signal that the cell storage buffer is not available in response to RxClk5. In response to RxClk6, the ATM layer device selects the address of the (Nxe2x88x921)th PHY layer device, which sends out that the cell send-out buffer is not available in response to RxClk7.
Hence, during the period of polling, the ATM layer device recognizes that the (N+3)th PHY layer device can send out the next cell. In part (c) of FIG. 8, 1F denotes a null address, and none of the PHY layer devices respond to the null address 1F.
When the 48th payload P48 is completely transmitted, as shown in part (e) of FIG. 8, the ATM layer device stops sending the transfer enable signal RxEnb* for the receive cell in response to TxClk8 (the signal RxEnb* is switched to the high level), and thus causes the PHY layer device to stop sending the cell data for the next clock cycle. At that time, that is, in response to RxClk8, as shown in part (c) of FIG. 8, the ATM layer device sends out the address N+3 of the next source PHY layer device.
The (N+3)th PHY layer device detects that the transfer enable signal RxEnb* for receive cell is stopped in response to RxClk9 (switches to the high level) and the address signal of the (N+3)th PHY layer device is sent out as the address signal, and recognizes that sending out of its own cell data is started. Then, the (N+3)th PHY layer device sends out cell data to the receive data signal line RxData.
The PHY layer devices having the addresses other than the address sent out in response to RxClk9 do not send cell data to the receive data signal line RxData. In the above-mentioned manner, the receive target PHY layer device is selected in response to RxClk9.
In response to RxClk9, as shown in part (e) of FIG. 8, the ATM layer device sends out the receive cell transfer enable signal RxEnb* (switches to the low level), and the PHY layer device #N+3 detects that the receive transfer enable signal RxEnb* is sent out in response to RxClk10. Then, as shown in part (f) of FIG. 8, the cell is sent out in the order of headers H1, H2, H3 and H4. Also, the signal RxSOC indicative of start of cell is switched to the high level as shown in part (g) of FIG. 8.
The PHY layer device #N+3 thus selected sends, as cell data, cell to the receive data signal line during the time when the receive cell transfer enable signal RxEnB* is being sent out (as long as it is at the low level). Further, during the above period, the polling is started again in synchronism with RxClk10 (which denotes the tenth rising edge of the receive clock signal RxClk).
Some ATM apparatuses which employ the Level 2 UTOPIA interface and is made up of a single ATM layer device and a plurality of PHY layer devices are described in U.S. Pat. No. 5,418,786 (class 370/94.2) and 5,485,456 (class 370/60). It is to be noted that the above Patents show a single-stage arrangement in which all PHY layer devices are connected to the single ATM layer device.
As described above, the Level 2 UTOPIA interface uses the 5-bit address signal, and required one of the five bits to be null. Thus, the upper limit on the number of PHY layer devices that can be connected to the ATM layer device is equal to 31. However, a large-scale access network apparatus required to accommodate a large number of subscribers is required that PHY layer devices over than the upper limit be connected to the ATM layer device.
In order to configure an ATM apparatus using PHY layer devices which conform with the Level 2 UTOPIA interface, such as an access network device capable of multiplexing and demultiplexing ATM cells, it is required to connect PHY layer devices in a multistage formation and enable a large number of PHY layer devices to be accommodated. Additionally, if a package which handles multiplexing and demultiplexing is segmented into parts of an appropriate size and such parts are connected in the multistage formation, an ATM apparatus having an appropriate scale can be constructed economically.
In a case where a plurality of PHY layer devices are connected in the multistage formation, there is only one destination when ATM cells are multiplexed and sent out towards the ATM layer device from the side of the PHY layer devices. That is, only one destination is the ATM layer network. In contrast, when cell data are distributed towards the PHY layer devices from the ATM layer device, the respective stages of the PHY layer devices are required to perform routing of cell data to respective transmit destinations.
Such routing may be accomplished as follows. The transmit address signal TxAddr output by the ATM layer device is used as routing information as it stands. The address of the PHY layer device is added to the routing information at each stage, so that the addresses of PHY devices are chained. However, the above routing cannot accommodate 32 PHY layer devices or more because only five bits of the transmit address signal TxAddr is available.
Another routing method may be used. Each PHY layer device which receives an ATM cell reads a VPI/VCI field in the cell header thereof and refers to a routing table in order to specify the routing destination. However, the above routing method requires that each PHY layer device be equipped with the routing table. This increases the circuit size. There is also another disadvantage that, if one of the routing tables is required to be modified, all of the other routing tables must be modified. This causes troublesome maintenance work.
The following documents disclose routing methods: Japanese Laid-Open Patent Application Nos. 1-190196, 1-240050, 1-289342 and 3-207140. However, the routings disclosed in the above Applications require a tag which is to be added to the head of each ATM cells, and is thus inconsistent with the routing using the address signal which conforms with the UTOPIA interface.
As to a packet routing method, an HIPPI technique is known (High-Performance Parallel Interface: see xe2x80x9cHIPPI I-FIELD PROPOSALxe2x80x9d, Network System Corporation (May 15th, 1990), Ideas on HIPPI I-field). According to the HIPPI, destination information named I-Field is transferred across a 32-bit data bus, and a shift operation within the I-Field is performed in each switching node. However, the above routing is not the routing using the address signal defined by the UTOPIA interface.
It is a general object of the present invention to provide an ATM apparatus in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide an ATM apparatus capable of multiplexing and demultiplexing a large number of ATM cells by using an address signal consistent with the UTOPIA interface and making it possible for each PHY layer device to have a simple routing process part.
The above objects of the present invention are achieved by an ATM apparatus comprising: an ATM device; and a plurality of devices arranged in a multistage formation in which the ATM device is located at a top of the multistage structure, the ATM device and the plurality of devices employing a given interface using an address signal and a control signal, and transferring routing information including address information on at least one of the devices by using the address signal and a data signal written into a given field of an ATM cell. Hence, a large number of devices such as PHY layer devices can be accommodated in the ATM apparatus.
The above ATM apparatus may be configured so that: the ATM device is equipped with a routing table in which the routing information is stored with regard to a value of a VPI/VCI field provided in a header of the ATM cell; and the devices arranged in the multistage formation extract the routing information using the address signal and the data signal in the given field of the ATM cell, and performs routing based on extracted routing information. The routing table is provided in the ATM device only. Hence, routing can be made with a simple structure. In addition, the maintenance work about routing can be done with ease. Further, the devices such as PHY layer devices are not required to have any table for routing.
The ATM apparatus may be configured so that the devices arranged in the multistage formation generates new routing information by a bit shift operation on the extracted routing information, and transfers the new routing information to another device of a lower stage. Hence, the routing information can be updated automatically and transferred to devices of the lower level without any difficulty.
The ATM apparatus may be configured so that the address signal and the data signal form a routing information field in which arbitrary information other than the routing information can be stored. Hence, desired information can easily be transferred to another device.
The ATM apparatus may be configured so that: the address signal and the data signal form a routing information field; the ATM device writes information on multicasting into the routing information field and transfers the information concerning multicasting to the devices of the lower stage; and each of the devices that receives the information concerning makes a copy of the ATM cell received and performs multicasting. Hence, multicasting can be accomplished with reduced traffic.
The ATM apparatus may be configured so that the address signal and the data signal form a routing information field in which arbitrary information other than the routing information can be stored, the arbitrary information being transferred between the ATM device and the devices of the lowermost stage of the multistage formation. Hence desired information can be transferred to another device with ease.
The ATM apparatus may be configured so that the given interface is a Level 2 UTOPIA interface. In this case, the given field is a user defined field of the Level 2 UTOPIA interface. Further, the ATM device is an ATM layer device of the Level 2 UTOPIA interface, and the devices arranged in the multistage formation are respectively physical layer devices of the Level 2 UTOPIA interface.
Another object of the present invention is to provide an ATM device applicable to an ATM apparatus including a plurality of devices arranged in a multistage formation in which the ATM device is located at a top of the multistage structure, wherein the ATM device and the plurality of devices employ a given interface using an address signal and a control signal, The ATM device comprises: an ATM switch which switches an ATM cell; and a routing table that stores routing information with regard to a value of a VPI/VCI field provided in a header of the ATM cell, the routing information including address information concerning at least one of the devices by using the address signal and a data signal written into a given field of the ATM cell.